Small logic transistors on an integrated circuit can be damaged by high voltages. Within an integrated circuit, placing a high voltage on the source or drain of a transistor with respect to the gate can cause the thin gate oxide of the transistor to break down. High static voltages can develop on the human body. High static voltages of two thousand volts can, for example, be generated when materials are rubbed together as a person walks across a room. If the person who is charged to the high static voltage were then to touch a terminal of an integrated circuit where another terminal of the integrated circuit is grounded relative to the person, then a high voltage would be impressed across circuitry within the integrated circuit in what is called an ESD (electrostatic discharge) event. This high voltage may burst through various parts of the circuitry within the integrated circuit and do damage. Such ESD events can occur in handling semiconductor products and can result in damage to the semiconductor products.
FIG. 1 (Prior Art) is a perspective view that represents an ESD event. A high voltage on a person 1 is transferred to a terminal 2 of an integrated circuit package 3. This voltage is in turn communicated through the package and to a pad of the integrated circuit within the package. Because circuitry on the integrated circuit may be at ground potential due to another terminal 4 of the package being grounded, the high voltage may be impressed across sensitive circuitry in the integrated circuit, thereby damaging the circuitry.
FIG. 2 (Prior Art) is a diagram of an example of an input buffer circuit 5 on the integrated circuit that can be damaged by the ESD event. Input buffer 5 includes a P-channel pullup field effect transistor (FET) 6, and an N-channel pulldown FET 7. When the high static voltage is conducted onto pad 8 due to person 1 touching terminal 2, then a high voltage is impressed across the gate-to-source of the N-channel pulldown transistor 7. This high voltage can destroy transistor 7 and render the integrated circuit inoperable.
FIG. 3 (Prior Art) is a circuit diagram of an example of ESD protection circuitry that is employed to protect the sensitive internal transistors of the input buffer. The ESD protection circuitry includes an ESD series resistor 9 and four ESD protection structures 10-13.
FIG. 4 (Prior Art) is a simplified cross-sectional diagram of ESD protection structure 13. Many variations on this structure exist in the prior art. The structure includes a first electrode 14, a lightly doped N− type ballast resistor structure 16 disposed between two N+ type regions 17 and 18, a polysilicon gate 19, a thin layer of gate oxide 20 between the gate 19 and a channel region 21, a second electrode 22, an N+ type source region 23, and a third electrode 24. N− and N+ type regions 17, 18 and 23 extend into a P type well region 25. Although not illustrated in the diagram of FIG. 4, a well contact electrode and a P+ type well contact region are typically provided so that well region 25 can be biased in a desired manner. First electrode 14 is coupled to node 26 in FIG. 3. Second and third electrodes 22 and 24 are coupled together and to ground node 27 in FIG. 3. When a high voltage of an ESD event is introduced onto pad 8 of the structure of FIG. 3, then a high voltage is communicated through resistor 9 and to first electrode 14. Second and third electrodes 22 and 24 are coupled to grounded terminal 4 of the integrated circuit package of FIG. 1. As a result, the voltage between electrodes 14 and 24 increases rapidly resulting in rapidly expanding depletion regions around regions 17, 16 and 18.
FIG. 5 illustrates the depletion regions with dashed boundary 28.
FIG. 6 is a simplified top-down diagram of the structure of FIG. 4. Some layers of the structure have been removed in order to simplify the illustration. Region 30 is a thick field oxide that surrounds the structure. Well contacts and a well contact region are provided to provide electrical contact with the well region, but the well contacts and well contact region are not shown in the simplified diagram of FIG. 6. The square symbols in FIG. 6 represent contacts between overlaying electrodes (not illustrated) and underlying structures 23, 19, 18, and 17. An implant blocking structure 31 is disposed approximately halfway in the horizontal dimension between the right edge of polysilicon gate 19 and the contacts to drain region 17. In the example of U.S. Pat. No. 6,100,125, the implant blocking layer is formed by blanket depositing a blocking oxide layer over the structure, and then using lithography and photoresist to etch away the other parts of the oxide layer, thereby leaving implant blocking structure 31 a substantial distance away from gate 19. Implant blocking structure 31 serves to block a subsequent N+ implant from highly doping the underlying ballast resistor 16.
FIG. 7 (Prior Art) illustrates an operation of the structure of FIG. 4. As the voltage between regions 17 and 23 increases during the ESD event, the depletion region 28 grows. The large electric field across this region causes an avalanche breakdown current to start flowing from region 18 to region 23.
FIG. 8 (Prior Art) is a graph of the source-to-drain current ID as a function of the source-to-drain voltage VD. The current ID is negligible as the voltage VD increases in range 32. The current ID then starts to increase due to the flow of avalanche breakdown current. This increase is within dashed oval 33.
A parasitic NPN bipolar transistor structure exists within the transistor structure of FIG. 4. The N+ type region 18 acts as the collector of this parasitic transistor. A portion of the N+ type source 23 acts as the emitter of the parasitic transistor. A portion of the semiconductor material between the N+ type region 18 and N+ type region 23 acts as the base of the parasitic transistor. FIG. 7 includes a bipolar transistor symbol that represents the parasitic NPN bipolar transistor. The avalanche current flowing between regions 18 and 23 increases to the point that some current flows into the base of the parasitic transistor. This current is illustrated by arrow 34 in FIG. 7. This base current is amplified by the NPN parasitic transistor, thereby causing the collector-to-emitter current to increase rapidly. This transistor action rapidly reduces the voltage VD back down to a safe voltage in what is sometimes called “snapback”, thereby preventing a large voltage from staying on electrode 14. In the graph of FIG. 8, the voltage VD is then effectively clamped to a lower VD voltage. Snapback reduces the voltage on node 26 and protects the transistors 6 and 7 of the input buffer.
The ESD protection transistor is a large device. A problem can exist where one small part of the transistor goes into snapback, but other parts of the transistor never experience enough avalanche current to turn on the parasitic bipolar transistor of those other parts. A solution is to provide the ballast resistance of region 16. Ballast resistor 16 serves to distribute current from the drain contact along the width of the transistor during an ESD event, thereby reducing local peak current density and allowing higher current density elsewhere so as to alleviate problems of non-simultaneous turn-on. See U.S. Pat. No. 6,100,125, U.S. Pat. Nos. 5,498,892 and 6,838,734 for further details. Implant blocking structure 31 is made approximately as long (in the left-to-right dimension of FIG. 9) as the poly gate 19 so that the underlying region 16 will be resistive enough to function as an effective ballast resistor. A typical resistance for a ballast resistor is about fifty ohms.
Unfortunately, the existence of the large electric fields associated with the large depletion regions that form in the snapback scenario can cause energetic electrons to be emitted from regions within the depletion region. The emission of these “hot carrier” electrons is illustrated in FIG. 9 by the arrows. Some of the hot carrier electrons are emitted such that they accumulate in the gate oxide 20. The result is a buildup of charge that can significantly change the threshold voltage of the transistor and eventually cause the transistor to be destroyed.
Multiple techniques exist in the prior art for moving the point of hot carrier injection away from the channel region such that hot carriers do not accumulate in the gate oxide. One technique is to perform a special implant step in the ESD protection transistors of the integrated circuit. See U.S. Pat. No. 6,838,734 for one variation on this technique. The special ESD implant step results in an area of lighter doping on the side of the drain region adjacent the channel region. As a consequence, the junction covered by the ESD implantation has a higher breakdown voltage, which is lower than the junction breakdown voltage at the junction under the drain contact. The breakdown location is therefore under the drain contact and is farther away from the channel region than in the structure of FIG. 9. Performing the ESD implantation step, however, entails adding processing steps to the overall semiconductor fabrication process because the ESD implant is only performed on ESD protection transistors and not on the ordinary logic transistors within the center of the integrated circuit. Furthermore, it is sometimes undesirable in the ESD protection transistor to have a lightly doped region immediately adjacent the channel region. An alternative process and structure is desired.